1. Field of the Invention
The invention relates in general to a control chipset of a computer motherboard, and more particularly, to a control chipset that supports various kinds of central processing units (CPU's) and a layout method thereof.
2. Description of the Related Art
As the personal computer rapidly develops, various kinds of CPU's are being manufactured. To comply with the variety of CPU's, motherboards able to support various kinds of CPU's are being developed. Further, because the processing speed of the CPU's continuously increases, signal transmission and reliability are of great concern to computer manufacturers. A good transmission quality results in better system performance and enhances reliability. Thus, how to fabricate a chipset with good signal transmission quality and reliability that supports various kinds of CPU's has become an important topic.
FIG. 1A and FIG. 1B are block diagrams showing a computer system accommodating a first type CPU and a second type CPU, respectively. Referring to FIGS. 1A and 1B, the chipset 110 (normally a north bridge chip, N/B) of a computer system can be coupled to a first type CPU 120 or a second type CPU 130, e.g., CPU 120 and 130 may be Intel PIII processor and AMD K7 processor, respectively.
Since Intel PIII processors require only one clock signal to perform data transactions with the N/B, while AMD K7 processor requires one input clock signal and one output clock signal to perform data transactions with the N/B, the output clock signal function is similar to the strobe signal. In the prior art, the N/B applied to the Intel PIII processor does not require an additional clock signal pin, while the conventional AMD K7 processor requires more than ten clock signal pins for the N/B. Thus, when designing a N/B applicable to both Intel PIII and AMD K7 processors, under the consideration of reserving I/O pin counts, the clock signal lines should share pins with other signal lines (such as the address (A/D) lines) via multiplexing mechanism.
FIG. 2 shows a conventional chipset that supports various CPU's. In FIG. 2, the chipset 210 is a north bridge including a first system logic circuit 220, a second system logic circuit 230, a first switch circuit 240, a second switch circuit 250, a first double defined signal pin 241, and a second double defined signal pin 251. The first system logic circuit 220 is applicable for the chipset coupled to an Intel PIII processor, while the second system logic 230 is applicable for the chipset coupled to the AMD K7 processor. When the chipset 210 is used for the AMD K7 processor, the first and second switch circuits 240 and 250 are used to control the connection switching between the first and the second double defined signal pins 241, 251 with the second system logic circuit 230. Meanwhile, the second double defined signal pin 251 is connected to the clock signal CLK of the second system logic circuit 230 via the second switch circuit 250.
FIG. 3 shows the second switch circuit 250 composed of transmission gates. Referring to FIG. 3, the second switch circuit 250 includes a first transmission gate 310 and the second transmission gate 320. The first transmission gate 310 has a first terminal connected to an address signal line (HA4 line), while the second transmission gate 320 has a first terminal connected to the clock signal line (CLK line). The second terminals of the first and the second transmission gates 310 and 320 are connected together for output. A control signal CTLA which indicates whether an Intel or AMD processor is coupled to the chipset 210 is used to control outputs of the second switch circuit 250. For example, HA4 line is selected when the control terminal CTLA is high, and the CLK line is selected when the control terminal CTLA is low.
The above circuit and layout design has some drawbacks. Basically, signals with the same character can share one pin for signal transmissions. The above switch circuits controlling the transmissions at the signal pins are used for the Intel PIII processor or the AMD K7 processor. However, if signals with different characters such as HA4 (address) and CLK (clock) in the second switch circuit 250 are multiplexed from a shared pin, e.g., the second double defined signal pin 251, unwanted crosstalk interference will be arisen during the signal transmission. As a result, the signal transmission quality is degraded. A conventional transmission gate is known as a non-ideal switch circuit for the north bridge chip. In high frequency applications, if a non-linear circuit device (such as a transmission gate or TTL) is used as the transmission path for switching signals, the capacitance-induction effect may introduce unexpected ground bounce noises, which significantly degrades signal quality.
The clock signal and strobe signal are very high frequency signals in comparison with others. Therefore, when applying the conventional design to the chipset supporting more than one CPU, crosstalk interference will be arisen when multiplexing a pin shared by several signal lines especially that every one of the signal lines is usually too close to its adjacent ones. Further, undesired ground bounce noises will also be introduced when the multiplex switch circuit is configured by using transmission gates, which seriously affecting the signal transmission quality